Generally, as semiconductor devices become highly integrated, widths of gate patterns and intervals between the gate patterns are reduced. Thus, technology for precisely and accurately forming small patterns is in demand. In a semiconductor device, a channel region of a transistor may become smaller and a contact resistance between a semiconductor substrate and a contact plug may be increased, because each of the gate patterns narrows in width proportional to shrinkage of a design rule. Thus, capacities of these semiconductor device may be effected.
To address this problem, methods of forming recessed gate structures having enlarged effective channel length and methods of forming elevated source/drain regions using a selective epitaxial growth (SEG) process have been developed. The methods of forming the elevated source/drain regions using the SEG process may improve characteristics of the semiconductor device by forming the source/drain regions in a silicon layer that may be formed by selectively growing silicon from an active region of a silicon substrate. However, in the SEG process, the silicon grows in a lateral direction simultaneously with in a vertical direction.
When the elevated source/drain regions are formed using the SEG process having the above-mentioned characteristic of the silicon growth, the silicon layers growing from the active pattern may be connected to each other. In other words, although the connection of the silicon layers is not generated in a peripheral region of the semiconductor substrate where the interval between the active patterns is wide, the silicon layers on the active patterns in a cell region of the semiconductor substrate where the active patterns are densely arranged may be connected with each other. Thus, there may exist a height limit of the elevated source/drain regions formed in the peripheral region of the semiconductor substrate caused by the densely arranged active patterns in the cell region of the semiconductor substrate. As a result, the characteristics of the transistor may not be improved.
To suppress the selective epitaxial lateral growth of the silicon during the formation of the elevated source/drain regions, methods of forming an isolating layer pattern, which is higher than the active pattern, may be proposed. According to the methods, a sidewall of the isolating layer pattern may be used as a blocking layer for reducing the likelihood that the silicon will grow in the lateral direction so that the silicon layers in the cell region may not be connected to each other. However, the isolating layer pattern on the semiconductor substrate may be partially removed by an ion implantation process and a process for removing a photoresist pattern, both of which are performed before the SEG process. As a result, the sidewall of the isolating layer pattern may not be sufficiently used as the blocking layer.